LiteCPU16
A 16-bit single-cycle processor written in Verilog. Not a simulator and not a teaching diagram — the register-transfer description of a physical microchip, stripped to the point where nothing is hidden.
The Design
- 16-bit data and address width
- Harvard architecture — separate instruction and data memory, so no structural hazards exist to work around
- Five instructions —
ADD,LW,SW,BEQ,NOP - Single-cycle execution. No pipelining, no caching, no interrupts.
Why Strip It This Far
Every omission here is deliberate. Pipelining, caches, and interrupts are what make real processors fast, and they are also what make a first processor unreadable. Remove them and the datapath becomes something you can follow end to end: fetch, decode, execute, write back, in one clock edge, with every wire visible.
Writing software on top of an abstraction is not the same as knowing what the abstraction is made of. This is the layer underneath the one everything else on this site runs on. ARCHITECTURE_GUIDE.md in the repo walks a single instruction through the datapath signal by signal.
Tech Stack
Verilog · digital design · RTL simulation